1. Field of the Invention
The present invention relates to a technology for designing a logic circuit in an LSI.
2. Description of the Related Art
The formation of clock trees and clock wirings are carried out after entire cells are completely located. In particular, upon completely placing the entire cells, with a view to satisfying limitations in timing of a clock signal, a location tool calculates a location of a clock buffer and paths of clock wirings in a way to minimize clock skew in a flip-flop (F/F).
As disclosed in Japanese Patent Provisional Publication No. 11-119853, a clock tree synthesis (CTS) processing is known as a procedure for minimizing clock skew in an F/F. By the “CTS processing” is meant that the F/Fs are divided into a plurality of clusters to allow the F/Fs, which belong to a particular cluster, to be connected in an equalized wiring distance while further connecting the plurality of clusters in the equalized wiring distance whereupon the plurality of clusters are further connected in the equalized wiring distance. Thus, the wiring processing is carried out in the equalized wiring distance in a connection from the F/F to a clock supply source and in bottoming up, minimizing clock skew in the F/Fs.
In the related art technology, a clock wiring delay between a buffer cell (hereinafter referred to as a “final stage buffer cell”), from which a clock is directly supplied to the F/Fs, and a clock input pin of each F/F is adjusted upon estimation and remains unchanged in a predicted value until detailed wirings are actually carried out, resulting in variations. Further, in relation to limitations in an output size of a final stage clock buffer and a location resource, it is extremely difficult to allow the final stage clock buffer to be evenly located with respect to any F/Fs and to perform clock wirings. Therefore, a major portion of clock skew occurs not in an area between the clock supply source and the final stage buffer but in an area between the final stage buffer cell and the clock input pins of the respective F/Fs. Further, in recent years, a remarkable speeding-up occurs in a semiconductor integrated circuit and a delay resulting from wiring resistance, accompanied by the miniaturization in a process, and wiring capacities are relatively higher than a cell delay. Accordingly, clock skew results in an increase in adverse affect on an operating speed of the semiconductor integrated circuit. In the meanwhile, an attempt has been undertaken to insert a delay cell as a measure against holds, resulting in an increase in a surface area of the semiconductor chip and a drop in the operating speed of the semiconductor integrated circuit.